1. Field of the Invention
The present invention relates to microcomputers (hereafter, referred to as “micros”) and in particular to a DMA (Direct Memory Access) device and a DMA transfer method incorporated in a micro.
2. Description of Related Art
With the aim of reducing load on CPU (Central Processor Unit) associated with increase in the number of peripheral I/Os (Input/Output Ports) incorporated in micros, there is demand for multichannel DMA. In general, a DMA device incorporates transfer information equivalent to the number of channels in DMA. Therefore, when the number of channels is increased, the amount of incorporated transfer information is increased and this leads to the expanded physical scale of the DMA.
As one means for avoiding the expansion of physical scale due to channel multiplication, there is a technique in which transfer information is placed in rewritable memory, such as RAM (Random Access Memory). At each time of transfer the transfer information is read from the RAM and the read information is placed in the DMA device to carry out DMA transfer.
In DMA of such a type that transfer information placed in RAM is read, the expansion of physical scale due to channel multiplication can be avoided. However, overhead due to reading of transfer information from RAM at each time of transfer is produced and this poses a problem of degradation in transfer performance.
In recent years, re-specification of data paths have been frequently carried out to cope with increase in micro clock frequency and this tends to increase clock counts in transfer. Because of bus multiplication in conjunction with diversification of peripheral I/Os and the complication of systems, it has been required to displace the access path from DMA to RAM to a different bus and overhead tends to further increase. For this reason, it is demanded to reduce overhead arising from reading of transfer information.
Description will be given to the configuration of a device disclosed in Patent Document (Japanese Patent Application Laid Open No. 2000-99452) with reference to FIG. 9, FIG. 10, and FIG. 11. As illustrated in FIG. 9, this device is comprised of: a first buffer including a DMA count register 91, a DMA command register 92, a DMA address register 93, a DMA offset register 94, and a request number register 81; a data bus 95 for carrying out data transfer; a transfer request signal 84; a request number 82 corresponding to the request signal 84; a request number comparator 83, and a DMA control circuit 99. This device is DMA of such a type that transfer information placed in RAM is read.
FIG. 10 illustrates an example of transfer information placed in RAM. One piece of transfer information is composed of transfer information TIA, TIB, TIC equivalent to 3 words. FIG. 11 illustrates an example of multiple pieces of transfer information placed in RAM. Transfer information items to be read are displaced in positions predetermined by a user program in the RAM like transfer information TIA000, TIB000, . . . .
Description will be given to the operation of the thus configured device. A transfer request is made by the transfer request signal 84. The request number corresponding to a transfer request signal 84 is given starting from the request number 82. At this time, at the request number comparator 83, the request number 82 is compared with a value stored in the request number register 81. Initially, the request number register 81 is empty and the result of comparison at the request number comparator 83 is disagreement. When the result of comparison is disagreement, the request number 82 is stored in the request number register 81 and transfer information corresponding to the request number 82 is read from the RAM.
First, transfer information TIA is read from the RAM and placed in the DMA count register 91 and the DMA command register 92. Subsequently, transfer information TIB and transfer information TIC are sequentially read from the DMA and placed in the DMA address register 93. Then DMA transfer is carried out.
When a transfer request whose request number is the same as the previous request number occurs, the request number 82 and a value stored in the request number register 81 are compared with each other at the request number comparator 83. Since the request number of the transfer request of this time is the same as the previous request number, the result of comparison is agreement. Therefore, reading of transfer information TIA, TIB, TIC is skipped and DMA transfer is immediately carried out.
When a transfer request whose request number is different from the previous request number occurs, the request number 82 and a value stored in the request number register 81 are compared with each other at the request number comparator 83. Since the request number of the transfer request of this time is different from the previous request number, the result of comparison is disagreement. Consequently, transfer information TIA, TIB, TIC are written back and saved to the RAM area corresponding to the previous request number because the transfer information TIA, TIB, TIC corresponding to the previous request number remain in the DMA device. Thereafter, the transfer information TIA, TIB, TIC corresponding to the request number 82 of this time are read and DMA transfer is carried out.
In the related art, as mentioned above, the request number comparator 83 determines whether or not to skip reading of transfer information according to whether or not the previous request number and the request number of this time are matched with each other.
FIG. 12 is a timing chart of an example where request numbers are matched with each other, illustrating how the effect of the related art is exerted. During period T0, first, request number 02 is inputted together with a transfer request. In response thereto, in the DMA device, request number 02 is set in the request number register 81 and transfer information TIA, TIB, TIC corresponding to request number 02 are read during period T02R. Thereafter, DMA transfer is carried out during period TDMA. When a request with request number 02, identical with the previous request number, occurs during period T1, the following processing is carried out: since the value in the request number register 81 and the request number in period T1 are identical with each other, reading of the transfer information TIA, TIB, TIC is skipped and the cycle in period TDMA is immediately carried out.
FIG. 13 illustrates an example where the previous request number and the request number are not matched with each other. In the related art, the following processing is carried out when a transfer request with request number 00 occurs during period T0: during period T00R, transfer information TIA, TIB, TIC corresponding to request number 00 are read and during period TDMA, DMA transfer is carried out. When a transfer request with request number 01 thereafter occurs during period T1, transfer information TIA, TIB, TIC corresponding to request number 00 is written back and saved during period T00W because request number 01 is different from the previous request number 00. During period T01R, transfer information items TIA, TIB, and TIC corresponding to request number 01 are read, and DMA transfer is carried out based on these items of transfer information.